1. Field of the Invention
The present disclosure relates to virtual memory and, more particularly, to a method and apparatus for caching of page translations for virtual machines.
2. Description of Related Art
An operating system is a set of computer programs that manage the hardware and software resources of a computer. Operating systems present to software applications the abstraction of virtual memory. The term virtual memory refers to a technique by which the physical memory of a computer, usually referred to as main memory, is not directly addressed, but is instead accessed via virtual addresses (logical addresses). This is achieved by placing the contents of the virtual memory on an auxiliary storage device and bringing parts of it into main memory, as required by an application, in a way that is transparent to the application. Virtual memory can be realized as page tables that store the translation from virtual addresses to physical addresses, wherein the translation function itself is processor platform dependent. Processors commonly cache the translation result in a translation look-aside buffer (TLB), which is a processor internal cache that is used to improve the speed of virtual address translation.
Hardware virtualization, commonly referred to as virtual machines, provides the illusion of one or more real machines to an operating system while providing access to virtual hardware resources. These include memory, processors and input/output (I/O) devices. Hardware virtualization can be realized using a virtual machine monitor (VMM) that presents to other software the abstraction of one or more virtual machines. The VMM is a software layer, which runs directly above the host hardware. The VMM contains emulation code that models the hardware behavior and further controls access to the actual resources of the real machine.
Virtualization of physical memory can be implemented by allocating and mapping parts of the machine's physical resources to a virtual machine (VM). The VM's guest operating system (guest OS), in turn, further partitions the memory between applications, data and the internal operations of the guest OS. This virtualization layer introduces a second translation layer for application memory allocated by the guest OS. The guest OS maintains page tables that translate from the application's virtual address space to the guest OS's physical address space. Additionally, the VMM translates from the OS's virtualized physical address space (“guest” physical addresses) to the machine's resources (host physical addresses). Hence, virtualization of memory requires two address translations: from guest-virtual to guest-physical memory and then from guest-physical to host-physical memory. For multi-level page tables each entry in a guest page table needs to be translated from guest-physical to host-physical addresses, effectively nesting a guest-physical to host-physical translation for each level in the table lookup.
Without requiring special hardware support, VMMs may be employed to generate and maintain an extra set of page tables, also referred to as shadow page tables, which translate guest virtual addresses into the host's physical addresses. These shadow page tables are derived from the guest OS's page tables and the VMM's resource allocation. However, the software model has a performance overhead due to the need for the VMM to maintain consistency between the real and the shadow page tables. This overhead is incurred by using status bits, such as accessed and dirty bits, which are co-located in the page tables. A number of software algorithms have been derived to minimize the overhead.
To achieve the nested translation without software intervention, it was proposed that virtualization-enhanced processors could perform the address translations. Such a model was proposed in the AMD (Advanced Micro Devices Inc.) “Pacifica” specification of its virtualization technology. In this approach, the VMM specifies a second memory address translation table that contains translations from guest-physical to host-physical memory. On a “TLB miss”, i.e., when memory is accessed and the mapping is currently not present in the TLB, the processor translates the guest-OS virtual address into a guest-physical address and after that, translates the guest-physical memory address into a host-physical memory address using the second translation table of the VMM.
In order to minimize memory footprint, page tables are structured in a hierarchy. As a result of the hierarchical structure, an address lookup has to perform multiple lookups until the translation is complete. That is, each lookup returns the address of the next level in the page table hierarchy until the translation is completed (or fails). In a non-virtualized environment, the references to the next level in the page table hierarchy are specified as physical addresses. When virtualizing a machine, the page table entries reference guest-physical memory. For a lookup, the processor has to translate the guest-physical memory address into a host-physical memory address before it can read the actual value. Thus the total number of required memory lookups depends on the number of levels of the guest-OS page tables and the VMM's page tables, which is the product of the guest-OS levels and host-OS levels.
With increasing virtual address spaces and supported physical memory, the number of levels of page tables increases. For example, when the OS page tables and the VMM page tables contain four levels, a page table lookup requires a total of sixteen memory references. In further virtualization extensions, this number grows quadratic with increasing virtualization layers.
There is a need for methods and apparatus for optimized address translations using nested multi-level page tables.